The present disclosure relates to a signal processing apparatus, a signal processing method and a communication apparatus and, more particularly, to a signal processing apparatus, a signal processing method and a communication apparatus that facilitate parameter control of filters.
In related-art receivers that select only a desired frequency by limiting the band of a reception frequency, a filter is used before or after a high-frequency amplifier. However, this filter possibly poses a fear of causing a deviation between the desired reception frequency and a filter tuning frequency (or cutoff frequency) due to process fluctuations of capacitors built in an LSI (Large Scale Integration) chip.
Such a deviation in a tuning frequency (or cutoff frequency) may deteriorate anti-interference or noise performance. Hence it is necessary for receivers to correct the filter capacitance fluctuations.
A method is known of correcting the filter capacitance fluctuations by checking codes of capacitor banks that are −3 dB on the low frequency side and the high frequency side of an entered test tone to select an intermediate code, for example, thereby correcting the capacitance fluctuations (for example, refer to US 2010/0130158A1, hereinafter referred to as Patent Document).
Another method is also known in which a negative Gm cell and an LC (Inductance-capacitance) tuning circuit are interconnected and a capacitor bank is adjusted so as to make a reception frequency which a PLL (Phase Locked Loop) synthesizer locked equal to an oscillation frequency of the LC tuning circuit, thereby correcting capacitance fluctuations, for example, (for example, refer to Sanghoon Kang, Huijung Kim, Jeong-Hyun Choi, Jae-Hong Chang, Jong-Dae Bae, Wooseung Choo and Byeong-ha Park, Samsung Electronics, Korea, “A Triband 65 nm CMOS Tuner for ATSC Mobile DTV SoC,” 2010 IEEE Radio Frequency Integrated Circuits Symposium, hereinafter referred to as Non-Patent Document).